The present invention relates to improvements of a quantizer-subtractor circuit of a two-step A/D converter.
A variety of types of A/D converters have been known. Of those types of A/D converters, the two-step A/D converter exhibits high-speed performance and a simple construction, as shown in FIG. 1, for example. An analog input signal Si is sampled and held by a sample/hold circuit 1. The held signal is input into a first A/D converter 2 and also into a minus input terminal (-) of a subtractor circuit 3. The first A/D converter 2 A/D converts the analog input to digital signals of 3 bits D6, D5, and D4. A D/A converter 4 D/A converts the digital signals D6-D4 and applies the converted ones to a plus input terminal (+) of the subtractor 3.
A second A/D converter 5 A/D converts the output signal of the subtractor 5 into digital signals of 4 bits D3-D0.
When the input signal Si takes a triangle waveform as shown in FIG. 2(a), the first A/D converter 2 produces digital signals of 3 bits D6-D4, as shown in FIG. 2(b). The D/A converter 4 converts such digital signals derived from the A/D converter 2 to an analog signal and applies it to the subtractor 3. Then, the subtractor 3 produces a signal taking a waveform as shown in FIG. 2(c). The second A/D converter 5 A/D converts the signal of FIG. 2(c) and produces digital signals D3-D0 of 4 bits, for example. The final A/D converted signal takes the digital form of 7 bits: the three upper bits of the first A/D converter 2 and the four lower bits of the second A/D converter 5.
A high speed converting operation is ensured when parallel-conversion type A/D converters are used for the A/D converters 2 and 5. The number of comparators required when the A/D converting operation is carried out in a two-step fashion is remarkably reduced as compared with parallel-conversion type A/D converter used in a one-step fashion. Therefore, the total A/D converter is simple in construction.
A circuit section containing the first A/D converter 2, the D/A converter 4, and the second A/D converter 6 can be simplified into a quantizer-subtractor circuit 6. This approach is found in "IEEE JOURNAL OF SOLID--STATE CIRCUITS" VOL. SC--14, No. 6, DECEMBER 1979, P938-943. The related part of the paper is expressly referred to in this specification. FIG. 3 is a circuit diagram of the quantizer-subtractor circuit which is shown on page 939, FIG. 2(a) in the above paper. FIGS. 4(a) and 4(b) correspond to the waveform diagrams of the input current Iin, and subtraction output voltage Vo, as shown in FIG. 2(b) on the same page. In operation of the circuit in FIG. 3, in response to an input signal, the input current Iin of an analog input current source 25 will vary as shown in FIG. 4(a). When the input current Iin is 0, equal currents I flow through transistors T1-T4. Therefore, resistors R1 and R2 with the equal resistance R have voltage drops of 2IR, respectively. Under this condition, the subtraction output Vo will be zero. When 0&lt;Iin&lt;I, all the currents I flow into a constant current source 21. With an increase of the input current Iin, the current of the transistor T1 decreases, and the current flowing through the resistor R1 also decreases. As a result, the subtraction output Vo increases, as indicated by the continuous line in FIG. 4(b). When I.ltoreq.Iin&lt;2I, the current I from the analog input current source 25 flows into the constant current source 21, turning off the transistor T1. increase of the input current Iin increases the current of the diode D1, while it decreases the currents flowing through the transistor T2 and the resistor R2. The result is a decrease in the voltage Vo, as indicated by a solid line in FIG. 4(b). A similar operation is repeated. When 2I.ltoreq.Iin 3I, an increase of the input current Iin increases the current of the diode D2. The current of the transistor T3 decreases, and no current flows into the transistor T1 and T2. When 3I.ltoreq.Iin&lt;4I, the current of the diode D3 increases with the increase of the input current Iin, but the current of the transistor T4 decreases. No current flows into the transistors T1-T3. The result is the plot of the subtraction output voltage Vo as indicated by a continuous line in FIG. 4(b).
For taking out an A/D converted output from this circuit, one of the possible approaches is to detect a voltage across the diode by a suitable means, for example, by comparators, to check a combination of the detected results by an encoder, and to produce an A/D conversion output signal. In this case, the A/D converted outputs D.sub.N and D.sub.N-1 encoded are: "00" when the diodes D1-D3 are all OFF; "01" when the diode D1 is ON, but the diodes D2 and D3 are OFF; "10" when the diodes D1 and D2 are ON, but the diode D3 is OFF; "11" when the diodes D1-D3 are all ON. This is illustrated in FIG. 4(c).
The subtraction output voltage Vo, as indicated by a solid line in FIG. 4(b), increases with an increase of the current Iin in the intervals 0.ltoreq.Iin&lt;I and 2I.ltoreq.Iin&lt;3I. It decreases with an increase of the input current Iin in the intervals I.ltoreq.Iin&lt;2I and 3I.ltoreq.Iin&lt;4I. In the case when the subtraction output voltage Vo is A/D converted by the second A/D converter (noted as 5 in FIG. 1) and the converted outputs are used as the lower bits, it is sufficient to invert the output bits in the intervals where the subtraction output decreases with the increase of the input current Iin (viz., where the A/D converted outputs D.sub.N and D.sub.N-1 of the quantizer-subtractor circuit are "01" or "11" and are used as the upper bits).
Alternatively, a couple of the quantizer-subtractor circuits of FIG. 3 may coupled with each other in a parallel fashion, followed by the combination of the encoder and the comparator, as shown in FIG. 3 on page 939 in the above paper. This alternative arrangement can provide three or more bits of the A/D converter. In a quantizer-subtractor circuit thus arranged, when Iin=4I, the current of 3I flows through the diode D1, the current of 2I flows through the diode D2, and the current I flows through the diode D3. In other words, different currents flow through the diodes D1-D3, respectively. This makes the current densities and the forward voltages of the diodes D1-D3 different. The result is that the cutoff point of each of the transistors T2-T4 changes or fluctuates. Accordingly, the A/D converted outputs D.sub.N and D.sub.N-1 change at the non-corresponding values of the input current Iin. In other words, the A/D converted output signal does not exactly correspond to a variation of the input current Iin. The waveform of the subtraction output voltage Vo is also deformed, as shown in FIG. 4( b), from its exact waveform.
One of the effective solutions to the cutoff-point shifting problem is to set the forward voltages at equal values. To effect this, the carrier storage effects of the diodes must be set equal to each other. This is realized as diode D1 is geometrically larger than diode D2, and that similarly diode D2 is geometrically larger than diode D3. More specifically, when Iin=4I, for example, the effective PN junction area of diode D1 is three times that of the diode D1; and the effective junction area of the diode D2 is two times that of the diode D3. In this approach, however, when Iin=3I, the forward voltages of the diodes are not equal. Therefore, the equalizing of the forward voltages of those diodes D1-D3 attained by this solution is a mere approximation.
The effective junction area of the PN junction finally changes depending on various conditions. For this reason, in manufacturing the diodes, it is very difficult to geometrically change the effective junction area of each diode D1-D3. Furthermore, when the number of diodes is increased with the increase of the bit number of the A/D conversion, equalizing of the forward voltages of those diodes is made even more difficult.